IPR
Topic 176 SICLD Act 2000
Topic 176 — Semiconductor Integrated Circuits Layout-Design Act 2000
This Module 20 opens FOUNDATIONAL EXTENSIONS — covering vital Indian IPR topics that warrant standalone treatment beyond the industry deep-dives. The SEMICONDUCTOR INTEGRATED CIRCUITS LAYOUT-DESIGN ACT 2000 (SICLDA) is India's SUI GENERIS framework — the "FORGOTTEN 8th IP" alongside Patents, Trade Marks, Copyright, Designs, GIs, PPV&FR varieties, and Trade Secrets/Confidential Information. Enacted 4 SEPTEMBER 2000 in compliance with TRIPS Article 35-38 obligations (which required member states to provide protection for layout-designs of integrated circuits per the WASHINGTON TREATY ON INTELLECTUAL PROPERTY IN RESPECT OF INTEGRATED CIRCUITS 1989 / IPIC TREATY). The Act establishes the SEMICONDUCTOR INTEGRATED CIRCUITS LAYOUT-DESIGN REGISTRY (SICLDR) under the MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY (MeitY) with headquarters in NEW DELHI. The framework protects the THREE-DIMENSIONAL ARRANGEMENT of transistors and circuit elements forming integrated circuits — the actual layout topology rather than the chip's functional output (which would be patent territory) or chip outer shape (which would be Designs Act territory). PROTECTION DURATION: 10 years from filing OR first commercial exploitation (whichever earlier) — non-renewable. ELIGIBILITY: layout must be ORIGINAL (creator's intellectual effort) + DISTINCTIVE (not commonplace among creators + manufacturers) + NOT COMMERCIALLY EXPLOITED anywhere in India or in a convention country. APPLICATION: Form LD-1; Registration fee ₹5,000; three sets of drawings/photographs of mask layout; GDS-II file format common; PDK information; submitted in TRIPLICATE physical form. PENALTIES: imprisonment up to 3 YEARS + fine ₹50,000 to ₹10,00,000 for willful infringement. India's SICLD Act is RAPIDLY GAINING RELEVANCE through the INDIA SEMICONDUCTOR MISSION (ISM) launched December 2021 with ₹76,000 crore allocation; SEMICON INDIA programme; Tata Electronics + Powerchip JV (Dholera Gujarat fab); Micron Technology Gujarat (Sanand) ATMP facility ₹22,516 crore approved June 2023; CG Power + Renesas + Stars Microelectronics OSAT facility; Kaynes Semicon. Recent strategic context: MAKE IN INDIA + AATMANIRBHAR BHARAT semiconductor self-reliance push; quantum chip development; specialised AI chip development; defense electronics (DRDO 2.0); 5G + 6G chip development. The framework integrates with: PATENTS ACT 1970 (chip functional aspects); DESIGNS ACT 2000 (chip outer appearance); COPYRIGHT ACT 1957 (chip design software/firmware); TRADE SECRETS (proprietary processes); IT ACT 2000 + DPDP ACT 2023 (data protection). This topic walks through every aspect of SICLD Act — registration framework, scope of protection, infringement, penalties, and India Semiconductor Mission integration.
1. Module 20 — Foundational Extensions Overview
176 SICLD ACT semiconductor IP — 8th IP | 177 CUSTOMS IPR enforcement at borders | 178 VALUATION IP valuation + damages | 179 COMPULSORY compulsory licensing depth |
180 IP CRIMES criminal enforcement | 181 DOMAIN INDRP + cybersquatting | 182 PUBLICITY personality + publicity rights | 183 IBC + IP insolvency + IP assets |
184 M20 MASTER foundational extensions closer |
2. The 8th Indian IP — SICLD Foundational Framework
A. The Eight Indian IP Statutes
IP Type | Statute | Year |
|---|---|---|
Patents | Patents Act | 1970 |
Trade Marks | Trade Marks Act | 1999 |
Copyright | Copyright Act | 1957 |
Designs | Designs Act | 2000 |
Geographical Indications | GI of Goods Act | 1999 |
Plant Varieties | PPV&FR Act | 2001 |
Trade Secrets | Common Law + ICA + IT Act | No standalone |
Semiconductor Layout-Designs | SICLD Act | 2000 |
B. The Statutory Provision Foundation
Section 2(g) SICLD Act 2000 — Layout-Design Definition "2. Definitions.—In this Act, unless the context otherwise requires— (g) \"layout-design\" means a layout of transistors and other circuitry elements and includes lead wires connecting such elements and expressed in any manner in semiconductor integrated circuits; (d) \"creator\" in respect of a layout-design means a person who creates the layout-design or, if more than one person creates the layout-design, the person who initiates and supervises the creation of the layout-design or causes the layout-design to be made; (h) \"original\", in relation to a layout-design, means a layout-design which is the result of its creator's own intellectual effort and is not commonplace among creators and manufacturers of layout-designs and semiconductor integrated circuits at the time of its creation; (o) \"semiconductor integrated circuit\" means a product having transistors and other circuitry elements which are inseparably formed on a semiconductor material or an insulating material or inside the semiconductor material and designed to perform an electronic circuitry function;" |
3. Eligibility + Originality Framework
A. Three-Pronged Eligibility Test
✅ SICLD Act — Eligibility Workshop THREE-PRONGED TEST FOR REGISTRATION: 1. ORIGINALITY (Section 2(h)) · Creator's OWN intellectual effort. · NOT mere copying. · NOT obvious arrangement. · Distinguishing skill + judgement required. 2. NOT COMMONPLACE · Among creators + manufacturers of layout-designs. · At the time of creation. · Industry-standard layouts excluded. · Routine arrangements excluded. 3. COMMERCIAL NON-EXPLOITATION · Not commercially exploited anywhere in India. · Not commercially exploited in any convention country. · Or commercial exploitation within 2 years (depending on interpretation). · Burden on applicant. SCOPE OF "LAYOUT-DESIGN": · Layout of transistors. · Other circuitry elements. · Lead wires connecting elements. · 3D arrangement. · Expressed in any manner. WHAT IS NOT PROTECTED: · Functional aspects (Patents Act territory). · Chip outer shape (Designs Act territory). · Embedded software/firmware (Copyright + Patents). · Manufacturing processes (Patents). · Trade secrets in design process. ORIGINALITY vs INVENTIVE STEP: · SICLD Act ORIGINALITY similar to Copyright concept. · Lower bar than Patent Act inventive step. · Skill + intellectual effort sufficient. · No requirement of "non-obviousness" in patent sense. KEY ELIGIBILITY CASES: · Limited Indian SICLD case law. · Reliance on copyright + patent precedents. · Comparative US Semiconductor Chip Protection Act 1984. · EU Topography Directive 87/54/EEC. · Japanese Semiconductor Layout-Design Act. |
4. Registration Procedure
A. Step-by-Step Registration Workshop
✅ SICLD Registration Workshop STEP 1 — APPLICATION: · Form LD-1. · Registration fee ₹5,000. · Paid via Demand Draft favoring "PAO, CGPDTM" payable at Mumbai. · Three sets of drawings + photographs of mask layout. · GDS-II file format (industry standard). · PDK (Process Design Kit) information. · Submitted in TRIPLICATE physical form. · SICLDR Mumbai office. STEP 2 — FORMAL EXAMINATION: · Registrar scrutinises completeness. · Compliance with Section 2(g) + (h). · Originality + non-commonplace assessment. · Documentation verification. STEP 3 — PUBLICATION: · Publication in Layout-Design Journal. · Public notice. · Opposition period opens. STEP 4 — OPPOSITION (Section 24): · 3-month opposition period. · Grounds: copying / lack of originality / commercial exploitation. · Hearing if requested. · Registrar decision. STEP 5 — REGISTRATION: · If no opposition / opposition rejected. · Certificate issued. · Registry maintained. · Validity 10 years. KEY DOCUMENTS: · Form LD-1. · Drawings/mask photographs. · GDS-II file. · PDK information. · Power of attorney (if agent). · Demand Draft. · Triplicate physical submission. KEY TIMELINES: · Examination: typically 6-12 months. · Opposition: 3 months from publication. · Registration: 12-18 months total. CREATOR ELIGIBILITY: · Indian national OR · National of country granting reciprocal protection OR · Principal place of business in India OR · Place of service in India. DURATION: · 10 years from filing OR first commercial exploitation (whichever earlier). · NON-RENEWABLE — distinct from other IPR. · Industry urgency for filing. |
5. Rights + Infringement Framework
A. Exclusive Rights Section 17
✅ SICLD Act — Exclusive Rights Workshop EXCLUSIVE RIGHTS (Section 17): 1. REPRODUCTION · Reproducing the layout-design. · In whole or substantial part. · In any form (physical or electronic). · Including incorporation in chips. 2. IMPORTATION · Importing chips with the layout-design. · Without authorization. · Goods incorporating the layout. 3. SALE + DISTRIBUTION · Selling chips with the layout-design. · Distributing in any form. · Commercial use. 4. COMMERCIAL EXPLOITATION · Profit-making activity. · Use by licensees framework. · Cross-border commercial activity. INFRINGEMENT (Section 18): · Reproduction without consent. · Importation/sale/distribution without consent. · Commercial exploitation without consent. · Wilful infringement criminal. FAIR USE EXCEPTIONS: · Private use. · Educational/research use. · Reverse engineering for analysis. · Independent creation. DOCUMENTATION: · File registration certificate. · Maintain creation records. · Digital + physical copies. · Cross-licensing arrangements. INTERNATIONAL FRAMEWORK: · TRIPS Article 35-38 protection. · Washington Treaty 1989 (IPIC) — India member. · US Semiconductor Chip Protection Act 1984. · EU Topography Directive 87/54/EEC. · Japanese semiconductor framework. · Reciprocal protection arrangements. |
6. Penalties + Enforcement
A. Civil + Criminal Framework
✅ SICLD Penalties Workshop CIVIL REMEDIES (Section 19): · Injunctions (interim + permanent). · Damages. · Account of profits. · Goods seizure + destruction. · Costs. CRIMINAL PENALTIES (Section 56): · Wilful infringement. · Imprisonment: 6 months to 3 YEARS. · Fine: ₹50,000 to ₹10,00,000. · Or both. · Cognizable offence. · Bailable offence. GRAVITY OF PENALTY: · Comparable to Trade Marks Act + Copyright Act criminal frameworks. · Higher than Designs Act framework. · Reflects strategic technology importance. ENFORCEMENT TOOLS: · Civil suit before HC (commercial division/IPD). · Criminal complaint to Police (Section 64-equivalent powers). · Customs IPR registration possible. · Interim injunctions framework. · Anton Piller orders for evidence. KEY CHALLENGES: · Limited Indian SICLD case law. · Comparative analysis from US/EU/Japan. · Complex technical evidence. · Reverse engineering proof. · Independent creation defence. · Cross-border enforcement. RECENT TRENDS: · Industry growth driving filings. · India Semiconductor Mission boost. · Increasing awareness. · Cross-licensing arrangements. · International collaboration. |
7. India Semiconductor Mission Integration
A. India Semiconductor Mission Framework
✅ India Semiconductor Mission (ISM) LAUNCHED DECEMBER 2021: · ₹76,000 CRORE allocation. · Comprehensive semiconductor ecosystem. · Make in India self-reliance. · Strategic technology focus. KEY COMPONENTS: 1. SEMICON INDIA PROGRAMME · 50% capital expenditure incentive. · Tata Electronics + Powerchip JV (Dholera Gujarat). · Micron Technology (Sanand Gujarat ATMP). · CG Power + Renesas + Stars Micro (Sanand OSAT). · Kaynes Semicon (Sanand). · Multiple OSAT facilities approved. 2. DESIGN-LINKED INCENTIVE (DLI) SCHEME · Indian semiconductor design. · R&D infrastructure support. · Talent development. · Patent + IP support. 3. SEMICON INDIA FUTURE DESIGN ROADMAP · Specialised AI chips. · 5G + 6G chips. · Defense electronics chips. · Quantum chip development. · Power electronics. 4. STRATEGIC PARTNERSHIPS · India-US iCET (Initiative on Critical and Emerging Technology). · India-Japan semiconductor cooperation. · India-EU semiconductor framework. · Australia-India critical materials. 5. TALENT DEVELOPMENT · India Semiconductor Workforce Development. · IIT specialised programs. · VLSI design training. · Industry partnerships. IP IMPLICATIONS: · SICLD filings expected to grow. · Patent filings semiconductor. · Trade secret framework. · Cross-licensing arrangements. · International IP coordination. MAJOR INDIAN PLAYERS: · Tata Electronics. · CG Power. · Kaynes Technology. · Vedanta-Foxconn (cancelled but strategic interest). · Various design companies. · ARM India (design hub). FOREIGN INVESTMENT: · Micron Technology US. · Foxconn Taiwan. · ST Microelectronics France-Italy. · Powerchip Taiwan. · Renesas Japan. · AMD US. |
8. International + Comparative Framework
A. International Framework
- Washington Treaty on Intellectual Property in respect of Integrated Circuits 1989 (IPIC Treaty).
- TRIPS Article 35-38 — international standard.
- US Semiconductor Chip Protection Act 1984 — first such law globally.
- EU Topography Directive 87/54/EEC.
- Japanese semiconductor IC layout-design law.
- South Korean integrated circuit topography law.
- China integrated circuit topography law.
B. Comparative Analysis
Aspect | India SICLD | US (1984) | EU (1987) |
|---|---|---|---|
Protection Term | 10 years | 10 years | 10 years |
Originality | Required | Required | Required |
Reverse Engineering | Allowed for analysis | Allowed | Allowed |
Reciprocal Protection | Convention countries | Bilateral | WTO members |
Penalties | ₹50K-10L; up to 3 yrs | Civil + injunctions | Civil + injunctions |
Independent Creation | Defence | Defence | Defence |
Industry Use | Growing rapidly | Mature | Mature |
9. Strategic Considerations
✅ For semiconductor companies — eight points For SICLD registration, file BEFORE commercial exploitation. For originality documentation, maintain detailed creation records. For cross-licensing, structure with multiple IP layers (patents + SICLD + trade secrets). For ISM benefits, leverage SICLD + DLI scheme integration. For international protection, register in convention countries. For infringement, leverage civil + criminal framework + Anton Piller. For reverse engineering, document independent analysis. For India Semiconductor Mission, integrate full IP strategy. |
10. Memory Aid — Quick Recall
✅ Quick Recall — SICLD Act SICLDA 2000 — enacted 4 September 2000. SICLDR — Mumbai-based registry under MeitY. TRIPS Article 35-38 + Washington Treaty 1989 (IPIC). Section 2(g) — layout-design definition. Section 2(h) — originality definition. Section 2(o) — semiconductor IC definition. 10 years protection (NON-RENEWABLE). Form LD-1; ₹5,000 registration fee. GDS-II file format standard. Triplicate physical submission. 3-month opposition period. Section 17 — exclusive rights. Section 18 — infringement. Section 19 — civil remedies. Section 56 — criminal penalties (₹50K-10L; 6 months-3 years). India Semiconductor Mission (December 2021) — ₹76,000 crore. Major players: Tata Electronics + Micron + CG Power + Kaynes. India-US iCET + India-Japan + India-EU semiconductor partnerships. |
🎯 EXAM POINTERS — TOPIC 176
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